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ICA-XFG-201 [PAID] Advanced Parsing and Deparsing
February 12 - February 13
ICA-XFG-201 is 2-unit advanced, instructor-led course module that offers detailed exploration of all aspects of packet header parsing and deparsing in P416/TNA. Course participants will learn how to define and parse complex packet headers in flexible, efficient, and robust manner that facilitates efficient processing in the match-action pipeline with proper handling and recovery from parser errors.
The course introduces several important concepts and coding techniques related to packet parsing and covers TNA-specific externs, available in the parser and deparser. The course also covers the topic of parser efficiency and discusses typical problems that can be encountered when writing a complex parser. This course is recommended to all data plane designers tasked with implementing non-trivial packet parsers.
ICA-XFG-201 is a part of Intel® Connectivity Academy XFG course series and can be taken either in-person or online.
Starting 12th February – 13th February – is a 2-unit course about advanced parsing and deparsing.
Upon the completion of the course, the students will:
1. Learn how to design packet headers that facilitate the most efficient processing in the match-action pipeline.
2. Learn how to parse complex headers with variable parts, including header stacks, variable length fields and user-defined fields with the emphasis on robustness and efficiency.
3. Learn how to process and recover from various parser errors.
4. Learn how to reuse complex packet parser code across ingress and egress processing.
5. Learn how to add run-time parser flexibility by using the value_set objects.
6. Learn how to perform incremental checksum updates using the Checksum() externs.
7. Learn how to recover from packet mis-parsing using resubmit.
8. Learn how to analyze parser efficiency using P4i tool and optimize it.
9. Learn how to debug parser and deparser errors.
Each unit consists of a 2-hour-long lecture (presentation) with one break and is followed by the hands-on labs.
This course is most suitable for data plane designers tasked with implementing P4 programs on Intel Tofino™ ASIC family devices.
To attend an online presentation, you will need to create a free Zoom account, associated with your work email address. Upon the registration, you will receive a link to the online event. You will also receive invitations to establish accounts on Slack and the P4ica Support Portal for lab support and materials access, also associated with your work email address.
JOIN THE FUTURE OF NETWORKING
As your trusted partner for all things P4 and Intel Tofino, STORDIS is thrilled to guide you on this transformative journey. Don’t miss this opportunity to dive into the future of networking and become a specialist in P4 development.
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